The present invention relates to a digital coding apparatus for use in compression of image data or the like.
Below, a description will be given to a typical method of compressing image data by means of a digital coding apparatus.
Initially, image data is divided into small blocks of about 8.times.8 pixels, which are then subjected to a two-dimensional discrete cosine transform performed by a discrete cosine transform circuit. The discrete cosine transform is a kind of orthogonal transformation whereby coordinates of the image data may be transformed from space coordinates to frequency coordinates.
In general, since only slight variations exist in the color or lightness of neighboring pixels in a natural image, its spatial frequency represented by the number of variations per unit distance is low. Consequently, individual elements of a transfer coefficient matrix obtained through the two-dimensional discrete cosine transform have large values if they represent low-frequency components. Conversely, if the individual elements of the transfer coefficient matrix represent high-frequency components, they have substantially zero values. By utilizing the above feature and coding in combination, compression of image data can be accomplished.
Next, from the transfer coefficient matrix, individual elements are sequentially read out as a DCT coefficient in the order in which the element representing the lowest-frequency component is read first. FIG. 11 shows the order in which the components of the DCT coefficient are read out from the transfer coefficient matrix. In the transfer coefficient matrix, the uppermost leftmost element represents the lowest-frequency component, while the lowermost rightmost element represents the highest-frequency component. The elements diagonally arranged therebetween represent increasingly higher-frequency components as they become closer to the lowermost rightmost element. The uppermost leftmost element is read out as a DC coefficient, followed by zigzag scanning, thereby sequentially reading out the other elements as AC coefficients. FIG. 11 shows the case where image data of 8.times.8 pixels is inputted. In the drawing, the DCT coefficient consisting of one DC coefficient and sixty-three AC coefficients has been outputted.
The above DCT coefficient is quantized by a quantize circuit, resulting in a quantized DCT coefficient.
Next, a variable-length coding circuit (hereinafter referred to as a VLC circuit) codes the DC coefficient into a DC code, while coding the AC coefficients into AC codes. In the process, variable-length Huffman coding is used.
Finally, a fixed-length data generating circuit generates fixed-length data from the DC code and AC codes and outputs it.
FIG. 7 is a block diagram showing the respective internal structures of the VLC circuit and of the fixed-data generating circuit in a conventional digital coding apparatus. In the drawing are shown: a VLC circuit 10; a judge circuit 11; an AC coding circuit 12; a DC coding circuit 13; a fixed-length data generating circuit 20A; a padding circuit 21 to fixed-length data; a first data write circuit 25; a first memory (RAM1) 26; a data holding circuit 27; a second memory (RAM2) 28; and a second data write circuit 29.
A description will be given of the operation of the circuit shown in FIG. 7. Here, it is assumed that the DCT coefficient as shown in FIG. 11 is inputted.
The judge circuit 11 judges whether each of the components of the inputted DCT coefficient is the DC coefficient or the AC coefficient and outputs the AC coefficients to the AC coding circuit 12, while outputting the DC coefficient to the DC coding circuit 13.
The AC coding circuit 12 detects a sequence of zero-valued AC coefficients and replaces them by a code representing the number of the consecutive 0s. Thereafter, the AC coding circuit 12 transforms the AC coefficients to variable-length Huffman codes and outputs them as AC codes.
The DC coding circuit 13 transforms the DC coefficient to a DC code and outputs it. However, in the case where the DC coefficient is used as it is as the DC code without being transformed, the DC coding circuit 13 becomes unnecessary.
The padding circuit 21 pads fixed-length data compactly with the variable-length AC code or AC codes in sequence.
The first data write circuit 25 writes the fixed-length data of AC code in the first memory 26.
The operation described above is performed by pipeline processing controlled by each clock.
The data holding circuit 27 stores in the second memory 28 the DC code outputted from the DC coding circuit 13 during the pipeline processing.
After the pipeline processing is temporarily suspended, the second data write circuit 29 stores in the first memory 26 the DC code read from the second memory 28 by the data holding circuit 17. At this point, since the sequential AC codes have been stored as fixed-length data in the first memory 26, the DC code should be placed so as not to overlap the AC codes.
FIG. 8 is an operational timing chart in the case where the conventional digital coding apparatus generates fixed-length data. In the drawing are shown: the second memory 28; a period 1 DCT required to process one DCT coefficient; and block units A, B, C, and D in accordance with which the pipeline processing is performed in the digital coding apparatus.
Upon the inputting of the DCT coefficient, the data holding circuit 17 initially stores the DC code in the second memory 28. On the other hand, the AC codes are sequentially processed by the pipeline processing so as to generate the fixed-length data of AC code. The number of clocks required to complete 1 DCT of pipeline processing is 64, which is equal to the total number of the DC coefficient and AC coefficients. The above processing is performed with respect to the plurality of DCT coefficients sequentially inputted.
When an image processing apparatus which receives data from the digital coding apparatus enters a blanking period, the DC code stored in the second memory 28 is read out by the data holding circuit 27 by non-pipeline processing. The read DC code is written by the second data write circuit 29 in the first memory 26 so as to generate the fixed-length data of DC code. FIG. 8 illustrates an example in which the image processing apparatus enters the blanking period every 15 DCTs. In this case, the number of DC codes to be processed during the blanking period is 15, while the number of clocks required by the non-pipeline processing is 15.
FIG. 9 is a view representing the content of the fixed-length data generated by the conventional digital coding apparatus and stored in the first memory 26. In the drawing is illustrated the case where the number of items of fixed-length data is the largest, i.e., where the number of the AC codes is 63 and the code length of each of the 63 AC codes is maximum. In this case, the fixed-length data generated from one DCT coefficient is composed of one DC code, 63 AC codes, and an EOB code representing the end position of the AC codes. If it is assumed that the storage area for one item of fixed-length data is 1 word, the largest number of items of fixed-length data generated from one DCT coefficient is 65 words.
FIGS. 10 are views representing the content of another example of fixed-length data generated by the conventional digital coding apparatus. As shown in FIG. 10(a), when the DCT coefficient in which all the AC coefficients except the 63rd one are zero-valued is given, the number of items of fixed-length data becomes 3 words as shown in FIG. 10(b).
However, the conventional digital coding apparatus has the following problems.
Since the conventional digital coding apparatus separately performs the AC code processing and the DC code processing in the fixed-length data generating circuit 20, it is disadvantageously increased in circuit scale. Moreover, since the AC code processing is pipeline processing and the DC code processing is non-pipeline processing, extra clocks are required, which disadvantageously increases power consumption.
Moreover, since the DC code processing is performed by utilizing the blanking period of the image processing apparatus, the conventional digital coding apparatus presents no problem in the case where it is applied to a display unit such as a monitor. However, in the case where data is accumulated in a storage medium such as a video memory, the DC code processing requires a period substituting for the blanking period, which presents a serious problem to higher-speed processing.
Furthermore, if the DC code processing as well as the AC coding processing is to be performed by pipeline processing in the conventional digital coding apparatus, it is difficult to retain compatibility with the structure of the apparatus associated with processing prior or subsequent to the pipeline processing. For example, since the largest number of items of fixed-length data generated from one DC coefficient and 63 AC coefficients become 65 words due to the presence of the EOB code in the case shown in FIG. 9, it follows that one DCT coefficient requires 65 clocks to be processed, which causes a time lag between the process of generating the DCT coefficient in the previous stage and the process of generating the fixed-length data. Moreover, since the EOB code is stored in 1 word after the 63rd AC code has been generated in the case shown in FIG. 10, processing requires a total of 65 clocks.